Cadence Design Systems
RTL2GDS, Product Engineering Architect
Cadence Design Systems is hiring a RTL2GDS, Product Engineering Architect in SAN JOSE 10, United States of America. Posted September 26, 2026.
Job at a glance
- Company
- Cadence Design Systems
- Location
- SAN JOSE 10, United States of America
- Pay
- $178,500 – $331,500
- Workplace
- On-site
- Employment
- Full-time
- Sector
- Engineering & Technology
- Posted
- September 26, 2026
About the job
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This position presents an exciting opportunity within Cadence’s Digital and Signoff Group (DSG) for a Product Engineer. In this dynamic environment, you’ll collaborate closely with R&D, Application Engineering & product marketing teams to help drive the development of advanced chip design software tools. As a Product Engineer, you will serve as a key technical resource, providing place-and-route expertise to both Cadence customers and internal development teams.
Candidates should bring a strong motivation and energy, along with a thorough understanding of ASIC design methodologies across all stages of the RTL to GDSII flow. Hands-on experience with timing closure and PPA optimization at 7nm and below is essential. Your analytical strengths will be vital in diagnosing customer challenges and delivering well-organized solutions. Excellent communication skills are required to ensure clear and effective collaboration.
Responsibilities for this role include supporting Cadence’s digital products, tracking and resolving customer issues alongside R&D and release teams, and conducting design benchmarks. You will also develop innovative flows and methodologies tailored to customer needs.
To qualify, applicants must possess a
- BS in Electrical Engineering with at least seven years of experience in digital implementation as either a design or product engineer
- Candidates should demonstrate a solid understanding of VLSI physical design and timing analysis, including familiarity with clock tree synthesis, routing optimization, and silicon signoff challenges
- Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 7nm and below nodes is required
- Proficiency in scripting languages or AI tools for productivity enhancement will be considered an asset
- Strong verbal and written communication skills
The annual salary range for California is $178,500 to $331,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.